I2S clock freq precision/stability?

robiwan
Posts: 46
Joined: Sat Dec 07, 2024 11:36 am

I2S clock freq precision/stability?

Postby robiwan » Mon Mar 03, 2025 8:29 am

Running an ESP32-S3 with I2S PDM @48kHz sample rate, the CLK output should be 6.144 MHz, but measuring with an oscilloscope, it is closer to 6.17 Mhz which is a discrepancy of almost 0.5% (!!!)

Is this to be expected? Using the default clock initializer macros:

Code: Select all

    /* Step 2: Setting the configurations of PDM TX mode and initialize the TX
     * channel The slot configuration and clock configuration can be generated
     * by the macros These two helper macros is defined in 'i2s_pdm.h' which can
     * only be used in PDM TX mode. They can help to specify the slot and clock
     * configurations for initialization or re-configuring */
    i2s_pdm_tx_config_t pdm_tx_cfg = {
        .clk_cfg = I2S_PDM_TX_CLK_DAC_DEFAULT_CONFIG(sample_rate),
        /* The data bit-width of PDM mode is fixed to 16 */
        .slot_cfg = I2S_PDM_TX_SLOT_DEFAULT_CONFIG(
            I2S_DATA_BIT_WIDTH_16BIT,
            (stereo ? I2S_SLOT_MODE_STEREO : I2S_SLOT_MODE_MONO)),
        .gpio_cfg =
            {
                .clk = PDM_TX_CLK_IO,
                .dout = PDM_TX_DOUT_IO,
                .invert_flags =
                    {
                        .clk_inv = false,
                    },
            },
    };
    pdm_tx_cfg.slot_cfg.hp_en = false;
    ESP_ERROR_CHECK(i2s_channel_init_pdm_tx_mode(tx_chan, &pdm_tx_cfg));

robiwan
Posts: 46
Joined: Sat Dec 07, 2024 11:36 am

Re: I2S clock freq precision/stability?

Postby robiwan » Sun Mar 09, 2025 7:17 am

The i2s_pdm debug log:

D (535) i2s_pdm: Clock division info: [sclk] 160000000 Hz [mdiv] 2 [mclk] 79872000 Hz [bdiv] 13 [bclk] 6144000 Hz

Question: How is 160000000/2 = 79872000 ?? 160000000/2=80000000/13~=6153846 Hz for blck is closer to what I observe on the oscilloscope.

robiwan
Posts: 46
Joined: Sat Dec 07, 2024 11:36 am

Re: I2S clock freq precision/stability?

Postby robiwan » Mon Mar 10, 2025 8:25 am

Ok, so the ESP32-S3 supports 9-bit for a/b and 8-bit for N in 1/(N+a/b) and with N=2,a=1,b=312 160000000/(2+1/312)=79872000 and then divide by 13 = 6144000. I'll just double check that a/b actually are set correctly.

robiwan
Posts: 46
Joined: Sat Dec 07, 2024 11:36 am

Re: I2S clock freq precision/stability?

Postby robiwan » Mon Mar 10, 2025 12:45 pm


robiwan
Posts: 46
Joined: Sat Dec 07, 2024 11:36 am

Re: I2S clock freq precision/stability?

Postby robiwan » Mon Mar 10, 2025 5:28 pm

Yup. Removing that line yields:

I (31562) stats: Stats 'i2s' count: 374
I (31563) stats: Interval (us) : [2657, 2672] ~2666.64
I (31563) stats: Variance (us^2) : 0.61
I (31564) stats: Std Deviation : 0.78
I (32562) stats: Stats 'i2s' count: 374
I (32563) stats: Interval (us) : [2657, 2672] ~2666.64
I (32563) stats: Variance (us^2) : 0.61
I (32564) stats: Std Deviation : 0.78
I (33562) stats: Stats 'i2s' count: 374
I (33563) stats: Interval (us) : [2657, 2672] ~2666.64
I (33563) stats: Variance (us^2) : 0.61
I (33564) stats: Std Deviation : 0.78
...

MicroController
Posts: 2661
Joined: Mon Oct 17, 2022 7:38 pm
Location: Europe, Germany

Re: I2S clock freq precision/stability?

Postby MicroController » Mon Mar 10, 2025 10:30 pm

All right!

Now I'm just wondering what "background noise" is to be reduced by the slightly off frequency selection...

robiwan
Posts: 46
Joined: Sat Dec 07, 2024 11:36 am

Re: I2S clock freq precision/stability?

Postby robiwan » Tue Mar 11, 2025 6:22 am

Yeah, specifically with all the other sources of noise.... Although, to be fair, this is just an issue with the I2S PDM subsystem, which I have only for a Proof Of Concept design. Later on, I'll use a real stereo DAC.

Who is online

Users browsing this forum: Qwantbot and 1 guest