Logic analyzer on ESP32 for self-diagnostics

[blade77]

Thanks a lot! Static 40 MHz sample rate seems to work fine for my use case. I would also like to send packages at 40 MHz as a kind of automation. I will try to figure out how.

[blade77]

I had to do the following changes for slave mode (using external clock) on ESP32:

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gpio_matrix_in(SD_CLOCK_PIN, I2S0I_WS_IN_IDX, false);

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I2SX.conf.rx_slave_mod = 1;

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//    logic_analyzer_ll_set_clock(sample_rate);

It seems to capture sd interface signals stable with 20 MHz clock.

[ok-home]

It seems to capture sd interface signals stable with 20 MHz clock.

I'm glad it worked out for you ))

[blade77]

on a side note via commenting

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//    logic_analyzer_ll_set_clock(sample_rate);

actually default values will be applied according the ESP32 technical reference manual. The default values are equivalent with these lines

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   I2SX.clkm_conf.clkm_div_num = 4;
   I2SX.sample_rate_conf.rx_bck_div_num = 6;

... actually I don't get why does it work on 20 MHz in slave mode...

[ok-home]

on a side note via commenting

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// logic_analyzer_ll_set_clock(sample_rate);

actually default values will be applied according to the ESP32 technical reference manual. The default values are equivalent with these lines

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 I2SX.clkm_conf.clkm_div_num = 4; I2SX.sample_rate_conf.rx_bck_div_num = 6;

.... actually I don't get why does it work on 20 MHz in slave mode...

I haven't looked into slave mode in detail I can only assume that
I2SX.clkm_conf.clkm_div_num = 4; clk -> 160/4 = 40 mHz
I2SX.sample_rate_conf.rx_bck_div_num = 6; -> not used because you are feeding external clk to WS_IN, maybe 40 mHz is enough to steadily capture 20 mHz samples

cameraslave.JPG (30.09 KiB) Viewed 37257 times

[blade77]

Thanks a lot! It is a very useful hint that actually rx_bck_div_num is not used in parallel slave mode.

[dzungpv]

I use your project and it is great but 50k sample for ESP32 is limited with long signal.
It is possible to make sample with ESP32 to 128k like the project you mention in the github https://github.com/EUA/ESP32_LogicAnalyzer?

[ok-home]

the size is limited by the free memory of the application
the analyzer is made to capture data with minimal impact on the running application,
if you need more free memory, you can use cli mode

[ok-home]

Added support for ESP32P4

• Only CLI interface is supported

• Data reading in parallel mode 8/16 bit by LCD/CAM module, one GPIO is required for PCLK signal

• For sample rate less than 1 MHz, one LEDC channel is required

• You can select IRQ/ETM trigger mode, ETM mode requires one more additional free GPIO

• Maximum sampling rate does not depend on the number of channels and the type of memory for the buffer (Ram/Psram) and is 80 MHz (for PSRAM frequency = 200 MHz)

• The number of samples is limited only by the size of free memory (Ram/Psram), The maximum number of samples can be 32,000,000 for modules with a Psram volume of 32 Mbyte.

[Sprite]

Added support for ESP32P4

Not sure if you're interested, but if you squirrel around in the SDK a bit, you can potentially make the P4 go much faster, probably up to 200MHz or so. Very high-level view: At least the PARLIO peripheral can also accept an external clock signal; I think this is specced for up to 80MHz but it can actually go a lot faster. (Possibly the LCDCAM module can do this as well, I haven't checked.) Additionally, if you make the PSRAM use the system PLL rather than the MPLL, you free that up for use as a random clock generator. You can then abuse the 50MHz output pin intended for Ethernet PHYs to output the clock signal; connect the PARLIO/LCDCAMs clock input pin to the same pin and it'll run on that clock signal. (But do note that on some silicon revs of the P4, the MPLLs clock frequency isn't quite stable: you may want to look into using other PLLs for that.)