Access RTC Fast RAM from ESP32-S3 RISC-V ULP

[_mdma_]

Hello!

Does anyone know of a way to access RTC fast RAM from the ESP32-S3 RISC-V ULP? I understand that this isn't supported out of the box, where RTC slow RAM is the default storage for the program and data.

I've read that RTC FAST RAM is intended to be used by the MCU only (APP and PRO cores). But I wonder if this is due to a hardware limitation or just convention that this cannot be used by the ULP?

In my use case, the ULP would only access fast RTC RAM while the main MCU is in deep sleep, so there wouldn't be any contention between them.

Running code on the ULP, I have tried to directly access an address corresponding to the Fast RAM address in the MCU's memory map, like this:

Code: Select all

void increment_fast_counter() {
    volatile uint32_t* counter = (volatile uint32_t*)(0x600fe068);
    *counter = (*counter)+1;
 }

But this has no effect on the ULP, while the MCU can successfully increment the counter.

Is there some way to map RTC Fast RAM into the ULP's address space? If this isn't possible, I would be happy to know the limitations that prevent this.

Many thanks,
Mat.

[MicroController]

Is there some way to map RTC Fast RAM into the ULP's address space? If this isn't possible, I would be happy to know the limitations that prevent this.

The TRM says that the ULP can "Access up to 8 KB of SRAM RTC slow memory for instructions and data". And the architectural overview indicates that the RTC domain is isolated from the rest of the system via both an arbiter and the APB bus, so the hardware most likely has no way for the ULP to access other parts of the system.

[finnbentley]

Does anyone have insights on whether it's possible to access RTC fast RAM from the ESP32-S3 RISC-V ULP, given that it typically defaults to using RTC slow RAM? io games

I understand that RTC fast RAM is primarily intended for use by the MCU (APP and PRO cores), but is this limitation due to hardware constraints or is it more of a convention?

In my application, the ULP would only need to access the fast RTC RAM while the main MCU is in deep sleep, which should eliminate any contention for memory access. Has anyone explored this or found a workaround?

[krzychb]

This is a hardware limitation, not just a convention.
The ULP's accessible memory for code and data is strictly the 8 KB of RTC SLOW memory.

rtc-memory-access-esp32-s3.PNG (186.3 KiB) Viewed 137 times