SPI slave is not releasing the MISO line

[HEckardt]

Hi ESP Community,

I'm using a ESP32 WROOM 32D. I configured the SPI slave:

#define SPI_CS 5
#define SPI_MOSI 23
#define SPI_MISO 19
#define SPI_CLK 18

//Configuration for the SPI bus
spi_bus_config_t buscfg={
.mosi_io_num=SPI_MOSI,
.miso_io_num=SPI_MISO,
.sclk_io_num=SPI_CLK,
.quadwp_io_num = -1,
.quadhd_io_num = -1,
};

//Configuration for the SPI slave interface
spi_slave_interface_config_t slvcfg={
.mode=0,
.spics_io_num=SPI_CS,
.queue_size=3,
.flags=0,
.post_setup_cb=my_post_setup_cb,
.post_trans_cb=my_post_trans_cb
};



//Enable pull-ups on SPI lines so we don't detect rogue pulses when no master is connected.
gpio_set_pull_mode(SPI_MOSI, GPIO_PULLUP_ONLY);
gpio_set_pull_mode(SPI_CLK, GPIO_PULLUP_ONLY);
gpio_set_pull_mode(SPI_CS, GPIO_PULLUP_ONLY);


// for test it was configured with pull_up and pull_down too
gpio_set_pull_mode(SPI_MISO, GPIO_FLOATING);

//Initialize SPI slave interface
ret=spi_slave_initialize(RCV_HOST, &buscfg, &slvcfg, SPI_DMA_DISABLED);

It is working without any problems. But I want to use also some other SPI slaves (Memory, TouchPanelCtrl). These devices are working also without any problems, as long the ESP is not connected. When the ESP is on the bus, the ESP-MISO line is pulled down the level to the GND and is desurbing the communication. I measured the voltage on the ESP MISO pin and I could see, the voltage is about 0V. Even the ESP is not selected. From my point of view, the ESP MISO pin should be in the high impedance (3-state) in case the ESP-SPI is not selected. During this time it must be an input or the output is disabled. How I have to configure the MISO pin, that I can connect other SPI slaves to my master?

Thank you for your support.

Greetings
Henry

[wanckl]

Hi, Thank you for your report, and we can reproduce the issue now, it is same as an github issue https://github.com/espressif/esp-idf/issues/8638

Form simply try, there are 2 ways, enable DMA, or reduce MISO pin strength by

Code: Select all

gpio_set_drive_capability(buscfg.miso_io_num, GPIO_DRIVE_CAP_0);

We'll continuing on debugging the root issue, but give you a way for quick testing

[HEckardt]

Hi wanckl,

ok, I'll check it out. But I want to avoid the DMA (no 4 Byte alignment wanted). Hope the pin strength reduction works. Otherwise I take a hardware solution with a SN74LC1G125 to separate the ESP32 MISO from the bus when the ESP32 CS is not active.

[HEckardt]

Hi wanckl,

I made some tests. Here my test environment:



When the S1 is open and the strength of the ESP32 MISO pin is in default: the MISO of the EEPROM, TP_Ctrl is floating (about 2V). The ESP32 MISO is nailed to the ground.

During communication:
MISO signal of the ESP32



MISO signal of the EEPROM



MISO signal of the TP_Ctrl



When the S1 is closed:
MISO signal of the ESP32



MISO signal of the EEPROM, Level is about 1.8 V, PIC MCU is able to recognize



MISO signal of the TP_Ctrl, level is below 1 V, PIC MCU is reading zeros



Now the strength of the ESP32 MISO pin is in the weakest state:

MISO signal of the EEPROM



MISO signal of the TP_Ctrl



The voltage level is about 3V now. The PIC MCU is happy with these signals. But in the idle state the MISO level is still nailed to the ground. This is not the related to the requriments. I will include a SN74LC1G125 in the ESP32 MISO line, to be clear on the right side.

Thank you for your support.

Greetings
Henry

[HEckardt]

Hmmm.....

unfortunately the images are not inserted in the post above. So, I add a .zip file with the pictures.

where the ....Not is in the Name is when the S1 is not connected,

where the ....Con is in the Name is when the S1 is connected,

where the ....ConWeak is in the Name is when the S1 is connected and the ESP32 MISO pin is in the weakest state

Greetings
Henry

[wanckl]

Thank you for your trying and feedback!

But unfortunately, finally get info from the design team that the ESP32 is true has this issue on chip hardware, it is an old design and can't do any software workaround, we can only:
1. using esp32 spi slave without other devices on bus
2. or like what you do, add additional mux chip between esp32 spi and the bus

All other chips don't have this issue, but we'll add notice for esp32 then, thank you!