About some architectural features of s31

[andylinpersonal]

For bus system:
1. Does any bus master support hardware coherency?
2. Which memory supports AMO transactions, and from which core?

For HP cpu cluster:
1. Does CLINT of each HP core have their own builtin MTIME system timer?
2. Does the SIMD unit on HP core 1 support the same instructions as P4 (v3.x)?
3. Details of supported Supervisor-level ISA extensions. Datasheet only said “sv32 mmu”, but no other related S-level extensions were mentioned.
4. Are the Zicbo* native cache maintenance operation supported?

[bongjiajun]

Regarding bus system:
1. ESP32-S31 dual RISC-V cores share the same D-cache, so there is no separate inter-core D-cache coherency issue between the CPUs.
However, there is no hardware coherency protocol support for:
- I-cache / D-cache coherency
- CPU and DMA coherency
2. When DMA and other non-cpu bus masters access cached memory regions (SPIRAM), software-managed cache maintance is required
RISC-V atomic transactions (including AMO / LR-SC operations) are supported on shared memory regions such as:
- TCM
- SPIRAM

For HP CPU cluster:
1. The 2core share 1 CLINT timer, we don't have mtimer CSR to get timer value, need use memory access to read timer value.
2. Yes, same as P4.
3. Standard S-mode CSRs (stvec, satp, scount, etc.. ), and Interrupt SCLIC.
4. No.

[andylinpersonal]

Which DMAs support external memory, including descriptor (if applicable) and buffer?

1. AHB & AXI GDMA (supported)
2. LP AHB GDMA (?)
3. DMA2D (supported to psram)
4. SDIO (supported)
5. DWC2 (supported by p4 but ? for s31)
6. EMAC (supported by p4 but ? for s31)