Tell us about the new MMU architecture!

[Bryght-Richard]

What's new comparing ESP32-S3 to ESP32-S31 MMU-wise?

[andylinpersonal]

See the fresh datasheet, it's sv32 MMU, so we can expect for a full Linux on this chip.
The old "MMU" on S3 and other chips are still some sort of programmable flash / psram mapper, not a virtual memory system from the aspect of CPU. It still presents on esp32-s31 for interfacing with PSRAM and flash.
But whether Linux-based sdk, on at least the more powerful core 1, would be supported by official, is still unclear yet.
Most possible use case with a Linux would be a AMP system: core 0 runs a modified esp-hosted-ng, communicate with core 1’s Linux via some RPMsg stuff. The Linux runs a mature networking and multimedia stuff. The prototype system has been demonstrated by a Linux maintainer for Xtensa port, jcmvbkbc. But for such a heavy environment, we may need more PSRAM to unlock the full potential

[rudi ;-)]

See the fresh datasheet, it's sv32 MMU,

- Sv32 two-level page-table address translation
- Compliant with RISC-V Sv32 virtual memory scheme

However, it’s likely not what you think it is?

The ESP32-S31 datasheet mentions “Sv32 two-level page-table address translation” and being “compliant with the RISC-V Sv32 virtual memory scheme”.

But in the publicly visible parts of ESP-IDF, I only see the MMU used for Flash/PSRAM mapping (esp_mmu_map / external memory mapping). A full Linux-style RISC-V Sv32 MMU would typically require satp handling, page tables, and page fault support, none of which are exposed in the current ESP-IDF.

So from the official ESP-IDF alone, it’s not really possible to conclude that full Linux-style Sv32 paging is available yet. That said, maybe I’ve missed something deeper in the stack… or maybe it’s already being explored in someone’s playground build and just not widely surfaced yet - who knows

[vvb333007]

But in the publicly visible parts of ESP-IDF, I only see the MMU used for Flash/PSRAM mapping

Well, the ESP-IDF is written in a such way.. If you enable all memory protection and address translation then you have to rewrite esp-idf. FreeRTOS does not expect any address translation magic etc..

[Squonk]

It is strange that the S31 does include a full-blown MMU, which is not the case for the P4.

I really need someone to explain me the Espressif strategy and naming schemes.

[Sprite]

It is strange that the S31 does include a full-blown MMU, which is not the case for the P4.

I really need someone to explain me the Espressif strategy and naming schemes.

If you think that Espressif has some comprehensive strategy that already maps out chips 10 year into the future, you'd be wrong. (Otherwise we'd have called the 'original' ESP32 the ESP32-S1 or something.) We develop chips as they are needed and as the market demands and as we think may be useful for the software, and we also do not have an unlimited amount of engineers. I don't know the exact reason that the P4 does not have a MMU and the S31 has, but it might be as simple as the MMU needing so many design cycles that it simply wasn't ready for the P4.