General ESP32S questions

[The_YongGrand]

Hello there,

After reading the forums and the documentations, I have some questions about the ESP32 system.

1.) Do you have a full IDE for the ones with the FreeRTOS and such? When I checked the SDK in your Github, there are a lot of procedures for compiling and even loading the code into the system. Will there be a full IDE or I have to manually do this process? Also, do you have the manual for the FreeRTOS? It looks like the functions in that version of FreeRTOS is slightly different.

2.) On the datasheet it seems that the peripheral registers are not listed down yet. I assume you are going to add these in the datasheet soon?

3.) From the forums, I read that for expanding the Flash and the data memory to be effective, you guys have to come up with another new revision of that chip?

Thanks.

[ESP_igrr]

Regarding an IDE: we do have plans to build a development bundle based on Eclipse for Windows, but we don't have timeline for this yet.

That being said, the only (recurring) thing you need to do to build and flash is "make -j8 flash". Setting up Eclipse environment may take half an hour or so, but once you have done that, it's mostly clicking "flash" target that you need to do. There's a description of that in the docs: https://esp-idf.readthedocs.io/en/lates ... setup.html

Documentation of the changes to FreeRTOS functions should be part of 1.0 release.

Technical reference manual is being worked on (it's mostly translation and editing). We will be updating it with a few new chapters some time soon.

Regarding expansion of flash memory, there are no problems with that in the current chip revision. Memory mapping hardware which works with external SRAM does seem to have a bug which in some cases causes incorrect data to be written. It should be fixed in a new revision, but there is still some verification going on, so I can't give more details at this point.

[The_YongGrand]

Regarding an IDE: we do have plans to build a development bundle based on Eclipse for Windows, but we don't have timeline for this yet.

That being said, the only (recurring) thing you need to do to build and flash is "make -j8 flash". Setting up Eclipse environment may take half an hour or so, but once you have done that, it's mostly clicking "flash" target that you need to do. There's a description of that in the docs: https://esp-idf.readthedocs.io/en/lates ... setup.html

Documentation of the changes to FreeRTOS functions should be part of 1.0 release.

Technical reference manual is being worked on (it's mostly translation and editing). We will be updating it with a few new chapters some time soon.

Regarding expansion of flash memory, there are no problems with that in the current chip revision. Memory mapping hardware which works with external SRAM does seem to have a bug which in some cases causes incorrect data to be written. It should be fixed in a new revision, but there is still some verification going on, so I can't give more details at this point.

Hello,

Thanks for your help. Since it's a very new product, one of the retailers nearby me are manufacturing and selling the Gravitech ones - I may test whatever codes and the setup with the training board.

Also, the ESP32s is a dual-core - is one of the core dedicated to the WiFi & BLE related processing, and the other core for the basic processing? Or, are all the WiFi & BLE done in hardware and we can take advantage of both cores?

Plus, about the I2S audio - I believe that the DMA can be coupled into the I2S module to stream to the external I2S DAC? I wanted to try that too as a test program for an FM Synth I did some years back. Any examples I can share?

Thanks again.

[ESP_igrr]

Both cores are accessible to applications. You can user FreeRTOS xCreateTaskPinnedToCore function to start a task on one of the cores. WiFi and BLE stacks are currently initialized to use the first core, but you can still run things there, stacks won't take much CPU time unless you need very high throughput.
We have an I2S driver in pipeline. I can't give you exact date, but i hope it should be on Github in a week or two.

[The_YongGrand]

Both cores are accessible to applications. You can user FreeRTOS xCreateTaskPinnedToCore function to start a task on one of the cores. WiFi and BLE stacks are currently initialized to use the first core, but you can still run things there, stacks won't take much CPU time unless you need very high throughput.
We have an I2S driver in pipeline. I can't give you exact date, but i hope it should be on Github in a week or two.

Given the fact that the WiFi and BLE are software controlled, I can directly disable them and use those two cores, if I need this as a plain microcontroller? If that is so that will be very flexible for some who wants a heavy processing!

Also, I can't seem to see the RTC registers in the datasheet - I assume that your crew haven't started writing these yet, or I'm looking at it wrong? If there is the RTC inside, it should have registers where I can set the hour, seconds, and the calendar, like in other popular DS1307/DS3231 RTCs?

[ESP_igrr]

Yes, in fact you need to explicitly enable wifi or bt if you want to use them. If you don't need them at some point, you can use ESP32 as a normal MCU. In the current master there is a bug that even if you don't use wifi stack, it will still be linked into the application, but this is going to be fixed soon.

Regarding RTC: the thing called RTC in the ESP32 is much more than a real time clock (although it has one). It is a name used for a separate clock and power domain of the chip. It has a bunch of peripherals (GPIOs, timer, clock, ADC, touch, coprocessor). Documentation for all that is work in progress. But in the latest master the "clock" feature is exposed already. If you set time (using NTP, for instance) and then go into deep sleep mode, RTC will perform timekeeping, and upon wakeup you will be able to get up-to-date time using standard C library functions.

Internally, time is maintained in a 48-bit counter. There are a few clock options, but currently the only one which is exposed is the calibrated internal 150kHz RC oscillator. External 32kHz clock will be supported at around the same time as the RTC documentation will be ready.

[The_YongGrand]

Yes, in fact you need to explicitly enable wifi or bt if you want to use them. If you don't need them at some point, you can use ESP32 as a normal MCU. In the current master there is a bug that even if you don't use wifi stack, it will still be linked into the application, but this is going to be fixed soon.

Regarding RTC: the thing called RTC in the ESP32 is much more than a real time clock (although it has one). It is a name used for a separate clock and power domain of the chip. It has a bunch of peripherals (GPIOs, timer, clock, ADC, touch, coprocessor). Documentation for all that is work in progress. But in the latest master the "clock" feature is exposed already. If you set time (using NTP, for instance) and then go into deep sleep mode, RTC will perform timekeeping, and upon wakeup you will be able to get up-to-date time using standard C library functions.

Internally, time is maintained in a 48-bit counter. There are a few clock options, but currently the only one which is exposed is the calibrated internal 150kHz RC oscillator. External 32kHz clock will be supported at around the same time as the RTC documentation will be ready.

Great, that is extremely cool. Can I send a sample application code on your repository once I've figured out the I2S module? I want to demonstrate how extremely cheap and efficient your ESP32 on musical applications.

I know it's a tall order, but I do believe that maybe in the future you guys might come up with another ESPxx-module with an SDRAM inside? Some of us need more RAM, and I know that accessing to the external SPI RAM is much more slower than any parallel RAM, so there might be a need for those things (especially frame buffers for graphical applications).

I'm checking the forums regularly for more of the updates as I'm waiting for the Gravitech version to arrive.

[ESP_igrr]

Re example code — sure, we will consider any well written example for inclusion in esp-idf repository. We are also thinking about setting up a curated list of libraries written for ESP-IDF.

A module with extra SRAM has already been designed, it's layout is similar to the layout of WROOM32 module, just slightly longer. I can't say when it will be available for purchase though.

[The_YongGrand]

Re example code — sure, we will consider any well written example for inclusion in esp-idf repository. We are also thinking about setting up a curated list of libraries written for ESP-IDF.

A module with extra SRAM has already been designed, it's layout is similar to the layout of WROOM32 module, just slightly longer. I can't say when it will be available for purchase though.

Thanks for offering the space for us to put our sample code - it'll help the community to go further!

On the new module, is the extra SRAM being more than 1MB? I can guess it's probably a serial or a parallel external SRAM. And since you said that the form factor is slightly longer, I can assume it has more GPIO pins?

If the new module is available for beta testing, could I do a test with it (with the permission of course)?

[ESP_igrr]

Not 100% sure, but I think it was a 32 mbit PSRAM. I'll let you know if/when we have some for test.