SUMP Compatible ESP32 Logic Analyzer with RLE

[E.U.A.]

Yes, but somehow at buffer, each DMA samples looks swapped.
I mean s2 with s1, s4 with s3...

I believe ESP_igrr knows why.

Hi EUA,

Did you see this code ?...

[jgustavoam]

Since we are reading (RX) from I2S, ESP32 expect external clock not use internal derived one.
I pass this requirement via feeding a pin via generated external clock signal and routing to I2S clk pin. But after 20Mhz, it doesn't work proper.

Hi EUA,
I saw this on this topic:
https://github.com/espressif/esp-idf/issues/2251
The Specialist IGRR said:
"Frequencies above 20MHz do not work in I2S mode"
I want to test this...

[jgustavoam]

Than I will use extra ram buffer to expand sampling on it.
I am little sad about sampling speed which is limited to 20Msps.
I found that If I use QSPI interface, I can sample up to 80Msps 4bit but I am not sure if it supports such a long RX reception.
But found that Arduino-esp32 don't support QSPI DMA, yet.
Otherwise I plan to use Dual QSPI with DMA to archive 80Msps 8Bit device implementation.
If I found such a some sample, will try to implement it also.
Thanks!

I had already thought about it. Some options I think:

• use one or more SPIRAMs in parallel ( Do you know Burst mode?) I have two SPIRAMs 23LC1024 (128KB x 20 MHz only).
  But I think Espressif sells SPIRAM faster.

• use an old PC DIMM RAM module (for example 100 MHz - 128 MBytes). More complex because a need refresh data

[jgustavoam]

Hi EUA,
I'm trying to test your analyzer (PC - Windows 10).

• I used Arduino IDE V 1.8.10 to compile and flash my ESP32 Dev Kit module

• Run PulseView - version 0.4.1 (64 Bits)

• Crystal Oscillator 14.318 MHz at GPIO23

For reference only (to others):
https://sigrok.org/wiki/PulseView
Pulse View downloads:
https://sigrok.org/wiki/Downloads

You can use this patch https://sigrok.org/bugzilla/show_bug.cgi?id=1025 for PulseView/Sigrok work proper.

How can I apply this patch? Where?

I cannot configure the serial port at PulseView:

• Choose the Driver: OpenBenck Logic sniffer OLS ?

• Serial: COM5 (CP210X Silicon Labs - ESP32 serial port)

• OK - not accepted

Thanks.

[E.U.A.]

Hi jgustavoam,

You need to apply this patch to libsigrok gıt repo and rebuild lıbrary from source code. If you don't know hot to do it better to go for Serial2 way.

If you don't want to fight with building from source, you better to use enable USE_SERIAL2_FOR_OLS flag at ESP32_LogicAnalyzer.h and try to use external USB-TTL device from UART2 pins. Default speed for OLS port is 3Mbaud while using Serial2 interface. You can decrease/increase it as well. You probably also need to clear RX buffer before detection (with some programs like cutecom or via arduino serial ... by opening the port with defined speed and close it after.).
Than Pulseview will saw the device.

Good luck

[jgustavoam]

Hi EUA,
I have basic concepts about Linux, compilers, Libraries rebuilding, etc.
But I don't want fight with this. I think I will spend a lot of time doing this.

The second option seems to be simpler - using ESP32 Serial 2.
I still don't understand why I can't use Serial1 .

I'm studying your code. And I have some suggestions:

PLL clock has a frequency of 320MHz and PLL_D2 has a half - 160MHz.
In your code, you use this PLL_D2 frequency to set I2S clock.
I suggest that you review your calculations.

My calculation is for example (tested with oscilloscope):
viewtopic.php?f=18&p=55305#p55305

Code: Select all

// Configure Bit Clock configuration - ESP32 Tech Reference page 308 and 337
// fi2s = fpll / (N + b/a) = 160 MHz / (4 +(0/1) = 40 MHz  (using PLL_D2 clock)

  I2S0.clkm_conf.clkm_div_num = 4;                                      // I2S clock divider’s integral value >= 2
  I2S0.clkm_conf.clkm_div_b = 0;                                        // Fractional clock divider’s numerator value
  I2S0.clkm_conf.clkm_div_a = 1;                                        // Fractional clock divider’s denominator value
  I2S0.clkm_conf.clk_en = 1;                                            // I2S clock enable
  I2S0.clkm_conf.clka_en = 0;                                           // Set this bit to enable clk_apll

[E.U.A.]

Hi jgustavoam,

I still don't understand why I can't use Serial1 .

Okay. Than you will clearly understand why.
The reason is, generally, ESP32 development boards, at least that I have, has USB-to-TTL UART chip on the board that DTR line connected to reset pin of the module. Means, when you try to open com port, it resets due DTR signal switching. And when module resets, it need to boot and write some debug messages to terminal, (AFAIK there are no way to avoid them) like

Code: Select all

ets Jun  8 2016 00:22:57

rst:0x1 (POWERON_RESET),boot:0x16 (SPI_FAST_FLASH_BOOT)
flash read err, 1000
ets_main.c 371 
ets Jun  8 2016 00:22:57
...

Okay, what is the problem with that? Problem is libsigrok doesn't clear RX buffer when it try to scan device on serial line. For scan ols device, it just send "0x00" for 5 times than try to read 4 bytes and expect string like ALS1... But instead reads "ets " at first run for example since it's available on RX buffer... And continuous sending is doesn't solve the issue since ALS1 answer become "1ALS" due there are 2x remaining byte on RX buffer every time... My patch is just flushes RX buffer before scan...

Thanks for the suggestions. I thought on it. It looks like code is trying to capture for 40Mhz. But its really capture at 20Mhz. How do I know it? I count CPU clock between DMA samples and It's accurate for 20Mhz. Sigrok acts like if sampling clock is 20Mhz. Also 20Mbps UART signal spikes minimum width are just on 1 dot width instead of 2. All I can say that: it's working.

[Sprite]

I think you can suppress those messages by pulling GPIO15 low on boot.

[E.U.A.]

ESP_Sprite, thank you. I don't know this info.

jgustavoam, could you please try after clear RX buffer (with arduino serial or somethin) while pulling GPIO 15 down?
Probably it will work

[jgustavoam]

EUA,
Tomorrow I'm going on a vacation trip.
I'll be back on February 22.
As soon as possible, I will test your Logic Analyzer. I am very interested in doing that.
Thanks.