ESP32 Forum

Hi,

I downloaded the ESP-DSP package from
GITHUB:
https://github.com/espressif/esp-dsp

and it is quite well put together. In the
directories available therein I was able to
find the following processors supported
within this DSP package:

* The extension (_ae32) for ESP32 chip.
* The extension (_aes3) for ESP32s3 processor.
* The extension (_arp4) for esp32p4 processor.
* The extension (_ansi) is ANSI C

I am planning to use the risk-V based esp32c6
processor, is there any optimzed assembly code for
the risk-V architecture ?

Thanks.

I don't think so. All the other chips have some kind of SIMD instructions, so it makes sense to hand-roll assembly code for them (as the C compiler doesn't know of and wouldn't make use of those SIMD instructions). The -C series have plain RiscV-cores without any SIMD support, so it doesn't really make sense to hand-roll assembly for them; the compiler usually does a good enough job by itself when you use the ansi-c version.

Thanks for the clarification. That was helpful.