xtensa-esp32s3-espidf flash results in boot cycling

Goose-Ninja
Posts: 1
Joined: Thu Feb 27, 2025 3:57 pm

xtensa-esp32s3-espidf flash results in boot cycling

Postby Goose-Ninja » Thu Feb 27, 2025 4:05 pm

Code: Untitled.txt Select all


 USAGE ➜  cargo run --release
Finished `release` profile [optimized] target(s) in 0.29s
Running `espflash flash --monitor target/xtensa-esp32s3-espidf/release/s3-test`
[2025-02-27T15:46:18Z INFO ] Detected 2 serial ports
[2025-02-27T15:46:18Z INFO ] Ports which match a known common dev board are highlighted
[2025-02-27T15:46:18Z INFO ] Please select a port
[2025-02-27T15:46:19Z INFO ] Serial port: '/dev/cu.usbserial-110'
[2025-02-27T15:46:19Z INFO ] Connecting...
[2025-02-27T15:46:22Z INFO ] Using flash stub
Chip type: esp32 (revision v1.1)
Crystal frequency: 40 MHz
Flash size: 4MB
Features: WiFi, BT, Dual Core, 240MHz, VRef calibration in efuse, Coding Scheme None
MAC address: 3c:8a:1f:d5:22:6c
App/part. size: 406,512/4,128,768 bytes, 9.85%
[00:00:01] [========================================] 17/17 0x1000 [00:00:00] [========================================] 1/1 0x8000 [00:00:24] [========================================] 234/234 0x10000 [2025-02-27T15:46:51Z INFO ] Flashing has completed!
Commands:
CTRL+R Reset chip
CTRL+C Exit

ets Jun 8 2016 00:22:57

rst:0x1 (POWERON_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
configsip: 0, SPIWP:0xee
clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
mode:DIO, clock div:2
load:0x3fff0030,len:7104
load:0x40078000,len:15576
load:0x40080400,len:4
ho 8 tail 4 room 4
load:0x40080404,len:3876
entry 0x4008064c
I (31) boot: ESP-IDF v5.1-beta1-378-gea5e0ff298-dirt 2nd stage bootloader
I (31) boot: compile time Jun 7 2023 07:48:23
I (33) boot: Multicore bootloader
I (37) boot: chip revision: v1.1
I (41) boot.esp32: SPI Speed : 40MHz
I (45) boot.esp32: SPI Mode : DIO
I (50) boot.esp32: SPI Flash Size : 4MB
I (55) boot: Enabling RNG early entropy source...
I (60) boot: Partition Table:
I (64) boot: ## Label Usage Type ST Offset Length
I (71) boot: 0 nvs WiFi data 01 02 00009000 00006000
I (78) boot: 1 phy_init RF data 01 01 0000f000 00001000
I (86) boot: 2 factory factory app 00 00 00010000 003f0000
I (93) boot: End of partition table
I (97) esp_image: segment 0: paddr=00010020 vaddr=3c050020 size=03fd8h ( 16344) load
[b]E (106) esp_image: Segment 0 0x3c050020-0x3c053ff8 invalid: bad load address range
E (114) boot: Factory app partition is not bootable
E (120) boot: No bootable app partitions in the partition table[/b]
ets Jun 8 2016 00:22:57

rst:0x3 (SW_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
configsip: 0, SPIWP:0xee
clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
mode:DIO, clock div:2
load:0x3fff0030,len:7104
load:0x40078000,len:15576
load:0x40080400,len:4
ho 8 tail 4 room 4
load:0x40080404,len:3876
entry 0x4008064c
I (60) boot: ESP-IDF v5.1-beta1-378-gea5e0ff298-dirt 2nd stage bootloader
Using plain template generated via, unmodified
cargo generate esp-rs/esp-idf-template cargo

Flashing a ESP32-Cam via a CH340C Mother board, purchased with the device.

Can build and flash esp32c3 chips no issue.

Thank you in advance for any help, google searches have not provided much info

MicroController
Posts: 2672
Joined: Mon Oct 17, 2022 7:38 pm
Location: Europe, Germany

Re: xtensa-esp32s3-espidf flash results in boot cycling

Postby MicroController » Sat Mar 01, 2025 12:51 am

Firmware built for an ESP32-S3 will not work on an ESP32.

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