ESP32-D0WD-V3 - erase_flash - fatal error

[Feos80]

Hi guys,

i have 2 ESP32-D0WD-V3 where i cant delete the flash. Nothing is attached to the devboard (all pins are not used).

Log:
.\esptool.exe --chip esp32 --port COM4 erase_flash
esptool.py v4.8.1
Serial port COM4
Connecting....
Chip is ESP32-D0WD-V3 (revision v3.1)
Features: WiFi, BT, Dual Core, 240MHz, VRef calibration in efuse, Coding Scheme None
Crystal is 40MHz
MAC: ec:e3:34:ce:61:00
Uploading stub...
Running stub...
Stub running...
Erasing flash (this may take a while)...

A fatal error occurred: Packet content transfer stopped (received 8 bytes)

Console:
[08:18:14]ets Jul 29 2019 12:21:46
[08:18:14]
[08:18:14]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
[08:18:14]invalid header: 0xefffffff
[08:18:14]invalid header: 0xefffffff
[08:18:14]invalid header: 0xefffffff
[08:18:14]invalid header: 0xcfffffff
[08:18:14]invalid header: 0xefffffff
[08:18:14]invalid header: 0xefffffff
[08:18:14]invalid header: 0xefffffff
[08:18:14]ets Jul 29 2019 12:21:46

What am i doing wrong? Is the device dead? Any way to reanimate it?

Regards,
Feos


Edit: Hold S1, press and release S2, release S1:

[08:20:24]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
[08:20:24]invalid header: 0xefffffff
[08:20:24]invalid header: 0xefffffff
[08:20:24]invalid header: 0xefffffff
[08:20:24]invalid header: 0xefffffff
[08:20:25]invalid header: 0xefffffff
[08:20:25]invalid header: 0x6fffffff
[08:20:25]invalid header: 0xefffffff
[08:20:25]ets Jul 29 2019 12:21:46
[08:20:25]
[08:20:30]rst:0x10 (Rets Jul 29 2019 12:21:46
[08:20:30]
[08:20:30]rst:0x1 (POWERON_RESET),boot:0x3 (DOWNLOAD_BOOT(UART0/UART1/SDIO_REI_REO_V2))
[08:20:30]waiting for download

However, i still cant erase flash.


The flash_download_tool_3.9.8_w1 can read efuse and read the flash (64KB)


=== Run "summary" command ===
EFUSE_NAME (Block) Description = [Meaningful Value] [Readable/Writeable] (Hex Value)
----------------------------------------------------------------------------------------
Calibration fuses:
ADC_VREF (BLOCK0) True ADC reference voltage = 1086 R/W (0b10010)

Config fuses:
WR_DIS (BLOCK0) Efuse write disable mask = 0 R/W (0x0000)
RD_DIS (BLOCK0) Disable reading from BlOCK1-3 = 0 R/W (0x0)
DISABLE_APP_CPU (BLOCK0) Disables APP CPU = False R/W (0b0)
DISABLE_BT (BLOCK0) Disables Bluetooth = False R/W (0b0)
DIS_CACHE (BLOCK0) Disables cache = False R/W (0b0)
CHIP_CPU_FREQ_LOW (BLOCK0) If set alongside EFUSE_RD_CHIP_CPU_FREQ_RATED; the = False R/W (0b0)
ESP32's max CPU frequency is rated for 160MHz. 24
0MHz otherwise
CHIP_CPU_FREQ_RATED (BLOCK0) If set; the ESP32's maximum CPU frequency has been = True R/W (0b1)
rated
BLK3_PART_RESERVE (BLOCK0) BLOCK3 partially served for ADC calibration data = False R/W (0b0)
CLK8M_FREQ (BLOCK0) 8MHz clock freq override = 53 R/W (0x35)
VOL_LEVEL_HP_INV (BLOCK0) This field stores the voltage level for CPU to run = 0 R/W (0b00)
at 240 MHz; or for flash/PSRAM to run at 80 MHz.0
x0: level 7; 0x1: level 6; 0x2: level 5; 0x3: leve
l 4. (RO)
CODING_SCHEME (BLOCK0) Efuse variable block length scheme
= NONE (BLK1-3 len=256 bits) R/W (0b00)
CONSOLE_DEBUG_DISABLE (BLOCK0) Disable ROM BASIC interpreter fallback = True R/W (0b1)
DISABLE_SDIO_HOST (BLOCK0) = False R/W (0b0)
DISABLE_DL_CACHE (BLOCK0) Disable flash cache in UART bootloader = False R/W (0b0)

Flash fuses:
FLASH_CRYPT_CNT (BLOCK0) Flash encryption is enabled if this field has an o = 0 R/W (0b0000000)
dd number of bits set
FLASH_CRYPT_CONFIG (BLOCK0) Flash encryption config (key tweak bits) = 0 R/W (0x0)

Identity fuses:
CHIP_PACKAGE_4BIT (BLOCK0) Chip package identifier #4bit = False R/W (0b0)
CHIP_PACKAGE (BLOCK0) Chip package identifier = 1 R/W (0b001)
CHIP_VER_REV1 (BLOCK0) bit is set to 1 for rev1 silicon = True R/W (0b1)
CHIP_VER_REV2 (BLOCK0) = True R/W (0b1)
WAFER_VERSION_MINOR (BLOCK0) = 1 R/W (0b01)
WAFER_VERSION_MAJOR (BLOCK0) calc WAFER VERSION MAJOR from CHIP_VER_REV1 and CH = 3 R/W (0b011)
IP_VER_REV2 and apb_ctl_date (read only)
PKG_VERSION (BLOCK0) calc Chip package = CHIP_PACKAGE_4BIT << 3 + CHIP_ = 1 R/W (0x1)
PACKAGE (read only)

Jtag fuses:
JTAG_DISABLE (BLOCK0) Disable JTAG = False R/W (0b0)

Mac fuses:
MAC (BLOCK0) MAC address
= ec:e3:34:ce:61:00 (CRC 0xbf OK) R/W
MAC_CRC (BLOCK0) CRC8 for MAC address = 191 R/W (0xbf)
MAC_VERSION (BLOCK3) Version of the MAC field = 0 R/W (0x00)

Security fuses:
UART_DOWNLOAD_DIS (BLOCK0) Disable UART download mode. Valid for ESP32 V3 and = False R/W (0b0)
newer; only
ABS_DONE_0 (BLOCK0) Secure boot V1 is enabled for bootloader image = False R/W (0b0)
ABS_DONE_1 (BLOCK0) Secure boot V2 is enabled for bootloader image = False R/W (0b0)
DISABLE_DL_ENCRYPT (BLOCK0) Disable flash encryption in UART bootloader = False R/W (0b0)
DISABLE_DL_DECRYPT (BLOCK0) Disable flash decryption in UART bootloader = False R/W (0b0)
KEY_STATUS (BLOCK0) Usage of efuse block 3 (reserved) = False R/W (0b0)
SECURE_VERSION (BLOCK3) Secure version for anti-rollback = 0 R/W (0x00000000)
BLOCK1 (BLOCK1) Flash encryption key
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
BLOCK2 (BLOCK2) Security boot key
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
BLOCK3 (BLOCK3) Variable Block 3
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W

Spi Pad fuses:
SPI_PAD_CONFIG_HD (BLOCK0) read for SPI_pad_config_hd = 0 R/W (0b00000)
SPI_PAD_CONFIG_CLK (BLOCK0) Override SD_CLK pad (GPIO6/SPICLK) = 0 R/W (0b00000)
SPI_PAD_CONFIG_Q (BLOCK0) Override SD_DATA_0 pad (GPIO7/SPIQ) = 0 R/W (0b00000)
SPI_PAD_CONFIG_D (BLOCK0) Override SD_DATA_1 pad (GPIO8/SPID) = 0 R/W (0b00000)
SPI_PAD_CONFIG_CS0 (BLOCK0) Override SD_CMD pad (GPIO11/SPICS0) = 0 R/W (0b00000)

Vdd fuses:
XPD_SDIO_REG (BLOCK0) read for XPD_SDIO_REG = False R/W (0b0)
XPD_SDIO_TIEH (BLOCK0) If XPD_SDIO_FORCE & XPD_SDIO_REG = 1.8V R/W (0b0)
XPD_SDIO_FORCE (BLOCK0) Ignore MTDI pin (GPIO12) for VDD_SDIO on reset = False R/W (0b0)

Flash voltage (VDD_SDIO) determined by GPIO12 on reset (High for 1.8V, Low/NC for 3.3V)

Using the --trace parameter shows this:

(...)
TRACE +0.001 Write 14 bytes: c0000a04000000000014a0f53fc0
TRACE +0.006 Read 1 bytes: c0
TRACE +0.000 Read 11 bytes: 010a0200000010010000c0
TRACE +0.000 Received full packet: 010a0200000010010000
TRACE +0.004 command op=0x0a data len=4 wait_response=1 timeout=3.000 data=7c60f63f
TRACE +0.001 Write 14 bytes: c0000a0400000000007c60f63fc0
TRACE +0.005 Read 1 bytes: c0
TRACE +0.001 Read 11 bytes: 010a0200002004960000c0
TRACE +0.000 Received full packet: 010a0200002004960000
TRACE +0.003 command op=0x0a data len=4 wait_response=1 timeout=3.000 data=14a0f53f
TRACE +0.000 Write 14 bytes: c0000a04000000000014a0f53fc0
TRACE +0.006 Read 1 bytes: c0
TRACE +0.001 Read 11 bytes: 010a0200000010010000c0
TRACE +0.002 Received full packet: 010a0200000010010000
Erasing flash (this may take a while)...
TRACE +0.005 command op=0xd0 data len=0 wait_response=1 timeout=120.000 data=
TRACE +0.000 Write 10 bytes: c000d0000000000000c0
TRACE +0.003 Read 1 bytes: c0
TRACE +0.002 Read 8 bytes: 01d0020000000000


flash_id:

PS C:\temp\esptool-v4.8.1-win64\esptool-win64> .\esptool.exe flash_id
esptool.py v4.8.1
Found 1 serial ports
Serial port COM4
Connecting....
Detecting chip type... Unsupported detection protocol, switching and trying again...
Connecting..............
Detecting chip type... ESP32
Chip is ESP32-D0WD-V3 (revision v3.1)
Features: WiFi, BT, Dual Core, 240MHz, VRef calibration in efuse, Coding Scheme None
Crystal is 40MHz
MAC: ec:e3:34:ce:61:00
Uploading stub...
Running stub...
Stub running...
Manufacturer: 5e
Device: 4016
Detected flash size: 4MB
Flash voltage set by a strapping pin to 3.3V
Hard resetting via RTS pin...