ESP32 - Understanding IO_MUX_x_REG

[MaXwEllDeN]

Hello folks,

I'm trying to implement my own baremetal solution to setup the GPIO pins on ESP32, but unfortunately I've come up across a confusion when reading the SoC documentation.

I want to implement a generic function to get the IO_MUX_GPIOX_REG address, in order to properly control it.

Referring to the Register 6.34 section, we have the following description:



That shows on parenthesis how to calculate the register address relative to the IO MUX base, as specified by the section 6.13.2:

6.13.2 IO MUX Registers
The addresses in parenthesis besides register names are the register addresses relative to the IO MUX base
addresses provided in Table 3.3-6 Peripheral Address Mapping in Chapter 3 System and Memory. The
absolute register addresses are listed in Section 6.12.2 IO MUX Register Summary.

From the table 3.3-6, we have the IO MUX base address to be 0x3FF49000.

So, I was expecting that if, for example, I wanted the address for IO_MUX_GPIO0_REG, I should calculate 0x3FF49000 + 0x10 + 4 * 0, which is 0x3FF49010.

But instead, the IO_MUX_GPIO0_REG is mapped to 0x3FF49044 according to Table 6.12-2.



What I'm getting wrong about the formula on Register 6.34? There's any way to write one that generalizes it without having to write my own Lookup Table?

[Sprite]

You are correct and I don't think there's a way to do this without a lookup table. Per esp-idf/components/hal/esp32/include/hal/gpio_ll.h :

Code: Select all

// the address of esp32's IO_MUX_GPIOx_REGs are not incremented as the gpio number increments
(address are out of order)                                                                   
extern const uint8_t GPIO_PIN_MUX_REG_OFFSET[SOC_GPIO_PIN_COUNT];  

Note that this is a quirk of the original ESP32; from what I can see all later chips (ESP32-Sx, ESP32-Cx, ESP32-Hx etc) have the registers in the order you'd expect.

(Also note that in general, if you want to do barebones programming, I'd pick e.g. the ESP32-C3. The RiscV architecture is generally easier to work with and the chip in general has fewer quirks.)

[MaXwEllDeN]

You are correct and I don't think there's a way to do this without a lookup table. Per esp-idf/components/hal/esp32/include/hal/gpio_ll.h :

Code: Select all

// the address of esp32's IO_MUX_GPIOx_REGs are not incremented as the gpio number increments
(address are out of order)                                                                   
extern const uint8_t GPIO_PIN_MUX_REG_OFFSET[SOC_GPIO_PIN_COUNT];  

Note that this is a quirk of the original ESP32; from what I can see all later chips (ESP32-Sx, ESP32-Cx, ESP32-Hx etc) have the registers in the order you'd expect.

(Also note that in general, if you want to do barebones programming, I'd pick e.g. the ESP32-C3. The RiscV architecture is generally easier to work with and the chip in general has fewer quirks.)

Thank you Sprite for your clarification.

I think that I'm going to follow the LUT approach, since it's cleaner and straightforward.
Can you tell me then what this formula on the parenthesis is referring to?

Thanks for suggesting the ESP32-C3, I'll definitely give it a try later on. But for now, I'll stick with this SoC. It may have its quirks and caveats, but there's always something new to learn from situations like these.