Flush cache between cores?

[mvzxa5ltmvzdc]

From what I know, it is possible for one core of the ESP32 to read a different value from a memory address than the other, if either of them has the memory region in question in its cache.
Is there any available function that forces one or both cores to flush and/or reload all or some of the cached memory regions, or is there any other way to do so?
Also, how is it resolved internally when both cores write to the same address, or addresses within the same cache line, in quick succession?

[Sprite]

From what I know, it is possible for one core of the ESP32 to read a different value from a memory address than the other, if either of them has the memory region in question in its cache.

How do you 'know' this? In normal situations (i.e. using esp-idf or another supported sdk and accessing psram or internal memory) both cores share the cache, so there won't be any inconsistency.

Also not sure what your second question is about... writes in quick succession aren't much different than writes with a longer time between the two; the memory value will simply change.

[MicroController]

Note that the ESP32 doesn't have a "CPU cache". Both cores operate directly on the shared SRAM. (I assume there's some hardware arbiter in place to serialize concurrent physical accesses, but that happens fully transparently.)
"The cache" on an ESP32 usually refers to the part of the SRAM which is used as a cache for "external" memory, i.e. flash and optional PSRAM.

[mvzxa5ltmvzdc]

Note that the ESP32 doesn't have a "CPU cache". Both cores operate directly on the shared SRAM. (I assume there's some hardware arbiter in place to serialize concurrent physical accesses, but that happens fully transparently.)
"The cache" on an ESP32 usually refers to the part of the SRAM which is used as a cache for "external" memory, i.e. flash and optional PSRAM.

Oh, thanks for clearing this up! I guess what I heard was just wrong then.

[MicroController]

Maybe.
There are however cases where it may look like two concurrent tasks get out-of-sync with shared memory. This can happen when, in C or C++, memory is accessed concurrently without the compiler being made aware, in which case the compiler may remove memory accesses it deems unnecessary.