SPI Master - Last MISO bit sampled late?

[saden123]

ESP32 S3 / Devkit C
IDF release / 5.4.0, Win11, VSCode
PSU: USB
SPI to ADS1235 24bit DAC
MOSI GPIO_NUM_11
MISO GPIO_NUM_13
SCLK GPIO_NUM_12
SPI2_HOST
MODE 1
SPI f: 5MHz, have tried 500Hz to 8MHz
Default on everything else.

Sending a 2 byte command to the ADC: {a, b}
The data clocked in on MISO should be {0xff, a}
>=15ns after the last negative clock, the ADC sets MISO high as part of its protocol (DRDY). This drops when there is a sample ready.

Problem: The SPI Master seems to be sampling the DRDY level rather than the real data bit at last clock edge, so:
Sending a 2 byte command to the ADC: {a, b}
The data clocked in on MISO should be {0xff, a}, but is actually {0xff, a|0x01}
Data from the logic analyser shows pulses and timing is correct on the wire. And interprets the bits correctly.
ChatGPT and I have been around in circles on this and I cannot believe it's an IDF issue, but what else can it be?