ESP32-C5 common crystal for phase-coherent WiFi CSI — esp-crab hardware files missing

[ruben.crispino]

Hi Espressif team and community,

I am building an 8-node phase-coherent WiFi CSI channel sounder using ESP32-C5 and came across the esp-crab reference design documented in ESP-Techpedia:
https://docs.espressif.com/projects/esp ... ution.html

This is exactly what I need — the common crystal solution between multiple ESP32-C5 chips for RF phase synchronization. However, the hardware design files are not available in the GitHub repository (espressif/esp-csi/examples/esp-crab).

What I need:

1. The esp-crab schematic showing how the shared crystal is connected between the two ESP32-C5 chips. Specifically:
- Is the crystal shared passively (direct connection) or through a clock buffer/splitter?
- What happens to XTAL_N on the slave chip(s) — floating, AC-coupled to GND, or driven?
- Are there any series/shunt components between chips on the clock line?

2. Guidance on scaling from 2 chips (as in esp-crab) to 8 chips:
- Is a fanout buffer (e.g. TI CDCE906 or similar) recommended for 8 nodes?
- Are there matched trace length requirements?
- Does the internal oscillator amplifier need to be disabled on slave chips?

3. Clarification on CSI phase behavior with shared clock:
- Are there residual inter-chip phase offsets from independent PLL lock?
- Does the Wi-Fi stack apply any internal phase rotations to CSI output?
- Is there a hardware timestamp in wifi_csi_info_t tied to the shared clock domain?

Context:
This is for academic channel sounding research requiring cross-receiver phase coherence for AoA/MIMO processing. Independent crystals introduce inter-node CFO that is indistinguishable from channel phase, making distributed CSI comparison unreliable. The esp-crab approach of a shared crystal is precisely the right solution — I just need the hardware implementation details to scale it to 8 nodes.

I also note there is an open GitHub issue (#18493) reporting that CSI IQ buffer data is static on ESP32-C5 5 GHz channels — could you confirm whether this is fixed in the latest IDF release, as we intend to use 5 GHz for sounding?

Target chip: ESP32-C5 v1.2
ESP-IDF: latest stable

Thank you in advance — any pointer to the esp-crab hardware files or an engineer familiar with the design would be hugely appreciated.

[ruben.crispino]

How can someone have the espressif people replying in the various topics?