ESP32Features – What, How, Why, What-for: a reference for the four questions before any chip decision

[artkeller]

What's actually available?
14 currently available or announced models (ESP32, S2, S3, C2, C3, C5, C6, C61, H2, H4, P4, E22, H21, S31) as of July 2026, including the three announced since September 2025 (E22 Wi-Fi 6E, H21 BLE/802.15.4, S31 with Gigabit Ethernet). The comparison table lists architecture, SRAM, flash/PSRAM combinations, radios, and interfaces, pulled directly from the datasheets.

How do the models actually differ?
Not just specs side by side, but behavior — e.g. deep sleep: which models retain state in RTC SRAM vs. LP SRAM, which have a dedicated LP core instead of an ULP co-processor, and what that means for actual field power draw. Same approach for the security side: crypto accelerator, Secure Boot stage, flash encryption, post-quantum readiness — per model, not a blanket "it's secure" claim.

Why would one model (or combination) be the right choice?
A spec table alone doesn't answer this. So there's a reasoned strengths/weaknesses writeup per SoC, plus ten documented multi-chip combinations — each with an explicit rationale for why one model covers a gap in another (e.g. P4 without radio + C6 for connectivity, or C5 + H2 + P4 for staggered field-device/gateway/edge-compute topologies).

What is each model actually good for?
A suitability matrix across 50 typical application scenarios (smart home hub through industrial IoT gateway, wearables through service robotics), rated from "optimal" to "unsuitable" rather than vague recommendations.

https://github.com/artkeller/ESP32Features

I'm not affiliated with Espressif; this is community-maintained. Every figure is tied to a specific datasheet version, and where a datasheet doesn't state a value explicitly (e.g. some deep-sleep current figures for C61/H4), it's flagged as estimated rather than presented as fact. If anything is outdated, misread, or wrong, I'd genuinely like to know — corrections and PRs welcome.