有一个大概的猜测:
在不使用ADC/DAC时,全双工下,时钟信号是TX为master,RX为slave,TX和RX内部共享时钟信号,TX同时为RX和外部codec提供时钟信号,使得所有时钟同步
而在ADC/DAC模式下,TX和RX都是master,内部不共享时钟信号,导致时钟并不完全同步。
Search found 22 matches
- Thu Feb 17, 2022 4:17 am
- Forum: ESP-IDF 中文讨论版
- Topic: ESP32的I2S_ADC_DAC速率不一样
- Replies: 7
- Views: 15151
- Thu Nov 25, 2021 10:10 am
- Forum: ESP-IDF
- Topic: I2S driver for ESP32 is not working [IDFGH-5854]
- Replies: 23
- Views: 42903
Re: I2S driver for ESP32 is not working [IDFGH-5854]
Dear shailesh.korat,
You asked really good questions! Actually some answers already on the way, you will see them in programming guide soon.
A1 : dma_buf_count : The total number of descriptors used by I2S DMA to receive/transmit data. A descriptor includes some information such as buffer address ...
You asked really good questions! Actually some answers already on the way, you will see them in programming guide soon.
A1 : dma_buf_count : The total number of descriptors used by I2S DMA to receive/transmit data. A descriptor includes some information such as buffer address ...
- Wed Nov 24, 2021 6:49 am
- Forum: ESP-IDF
- Topic: I2S driver for ESP32 is not working [IDFGH-5854]
- Replies: 23
- Views: 42903
Re: I2S driver for ESP32 is not working [IDFGH-5854]
Hi shailesh.korat,
Glad to see you!
For the first question, here is the explanation for overtime_tick:
Meaning
1. Generally speaking, 'overtime_tick' is the ticks that 'i2s_read' should cost, that means, if the i2s_read task wait for more than 'overtime_tick', there must be data dropped.
2 ...
Glad to see you!
For the first question, here is the explanation for overtime_tick:
Meaning
1. Generally speaking, 'overtime_tick' is the ticks that 'i2s_read' should cost, that means, if the i2s_read task wait for more than 'overtime_tick', there must be data dropped.
2 ...
- Wed Nov 24, 2021 5:53 am
- Forum: ESP-IDF 中文讨论版
- Topic: ESP32的I2S同步时钟BCK最高输出时钟达不到手册标的40MHZ
- Replies: 3
- Views: 7868
Re: ESP32的I2S同步时钟BCK最高输出时钟达不到手册标的40MHZ
mr_jing 您好,
对于您提到的频率不准确的问题,是由时钟源造成的。使用较高采样频率时,PLL160M的时钟分频精度较差,而APLL时钟源能够产生一个更精确的频率,但由于驱动中APLL分频系数计算方式的局限性,目前对于高采样频率的支持不够好,我们会尽快修复该问题,感谢您的反馈!
Ps: 当使用APLL时,其最高支持128MHz,而从APLL分频得到MCLK至少为2分频,即MCLK <= 64MHz,一般MCLK到BCLK也至少是2分频,所以此时BCLK <= 32MHz
对于您提到的频率不准确的问题,是由时钟源造成的。使用较高采样频率时,PLL160M的时钟分频精度较差,而APLL时钟源能够产生一个更精确的频率,但由于驱动中APLL分频系数计算方式的局限性,目前对于高采样频率的支持不够好,我们会尽快修复该问题,感谢您的反馈!
Ps: 当使用APLL时,其最高支持128MHz,而从APLL分频得到MCLK至少为2分频,即MCLK <= 64MHz,一般MCLK到BCLK也至少是2分频,所以此时BCLK <= 32MHz
- Tue Nov 23, 2021 3:48 am
- Forum: ESP-IDF 中文讨论版
- Topic: ESP32的I2S同步时钟BCK最高输出时钟达不到手册标的40MHZ
- Replies: 3
- Views: 7868
Re: ESP32的I2S同步时钟BCK最高输出时钟达不到手册标的40MHZ
mr_jing 您好,
非常感谢您的反馈,请问能否提供一下这些,以便定位具体问题:
1. IDF版本
2. 文档关于BCK最高能到40MHz表述的具体段落
3. 使用的逻辑分析仪采样频率
-----------------------------------------
从提供的代码中发现i2s_config_t中的mclk_multiple字段并未设置,默认为256,由于BCLK是由MCLK分频得到,而MCLK由APLL或PLL160M分频得到,想要获得较大的BCLK,就需要设置较小的MCLK分频系数以及BCLK分频系数,MCLK的分频系数是自适应的,没法改变 ...
非常感谢您的反馈,请问能否提供一下这些,以便定位具体问题:
1. IDF版本
2. 文档关于BCK最高能到40MHz表述的具体段落
3. 使用的逻辑分析仪采样频率
-----------------------------------------
从提供的代码中发现i2s_config_t中的mclk_multiple字段并未设置,默认为256,由于BCLK是由MCLK分频得到,而MCLK由APLL或PLL160M分频得到,想要获得较大的BCLK,就需要设置较小的MCLK分频系数以及BCLK分频系数,MCLK的分频系数是自适应的,没法改变 ...
- Tue Nov 23, 2021 2:23 am
- Forum: ESP-IDF
- Topic: I2S driver for ESP32 is not working [IDFGH-5854]
- Replies: 23
- Views: 42903
Re: I2S driver for ESP32 is not working [IDFGH-5854]
Dear shailesh.korat,
Nice to hear your feedback! Seems you met another data lost problem, I need some time to test this issue, but recently I wrote a specific example for the data drop issue, you can have a try and hope it can help.
The key is to create at least two receive buffers, if one is ...
Nice to hear your feedback! Seems you met another data lost problem, I need some time to test this issue, but recently I wrote a specific example for the data drop issue, you can have a try and hope it can help.
The key is to create at least two receive buffers, if one is ...
- Wed Nov 10, 2021 11:53 am
- Forum: ESP-IDF 中文讨论版
- Topic: ESP32-C3 I2S接口支持PDM接收吗
- Replies: 4
- Views: 5274
Re: ESP32-C3 I2S接口支持PDM接收吗
目前PDM的支持情况是:
ESP32:TX RX
ESP32S2:不支持
ESP32C3:TX
ESP32S3:TX RX
ESP32:TX RX
ESP32S2:不支持
ESP32C3:TX
ESP32S3:TX RX
- Wed Nov 10, 2021 3:47 am
- Forum: ESP-IDF 中文讨论版
- Topic: ESP32-C3 I2S接口支持PDM接收吗
- Replies: 4
- Views: 5274
Re: ESP32-C3 I2S接口支持PDM接收吗
不支持,ESP32-C3仅支持PDM TX~
- Mon Oct 18, 2021 5:56 am
- Forum: ESP-IDF
- Topic: I2S driver for ESP32 is not working [IDFGH-5854]
- Replies: 23
- Views: 42903
Re: I2S driver for ESP32 is not working [IDFGH-5854]
@shailesh.korat
Sorry for the late reply~
Thank you very much for your significant information! After some experiments, I think I find the reason of data clip (in other word, data lost).
Actually, received data buffer length is not really related to the dma_buf_len, but is related to the sample ...
Sorry for the late reply~
Thank you very much for your significant information! After some experiments, I think I find the reason of data clip (in other word, data lost).
Actually, received data buffer length is not really related to the dma_buf_len, but is related to the sample ...
- Mon Sep 27, 2021 9:05 am
- Forum: ESP-IDF
- Topic: I2S driver for ESP32 is not working [IDFGH-5854]
- Replies: 23
- Views: 42903
Re: I2S driver for ESP32 is not working [IDFGH-5854]
Few days ago, a fix commit (a287f34f88e78759cf09d2d9018b49adb70ea6fd) for apll clock is updated to the github, you can have a try with both 'apll on' and 'apll off' condition on the latest master branch. If it still not working, I might need your register dump for debugging.