ESP32-C5-WROOM-1 Top Layer and 4 layer PCB layout

[Panometric]

I need some clarification on PCB design requirement for ESP32-C5-WROOM-1:

In the 2D download: https://www.espressif.com/sites/defaul ... rint_0.dxf there is a unusual declared "No GND copper only in top layer"

Yet, in the device datasheet: https://www.espressif.com/sites/default ... eet_en.pdf Section 11.1 and 11.2 does not mention this area, nor does https://docs.espressif.com/projects/esp ... esign.html

In the dev board https://dl.espressif.com/dl/schematics/ ... 250211.pdf it shows a gap in the top layer copper. but the bottom layer does have a GND pour in that area.

1. Which document is correct?
2. For a 4 layer board where layer 2 is solid GND and 7.8 mil away from top, is it OK to leave GND on layer 2?
3. IF NOT, Is it OK to locate components on the bottom in this area?
4. Should the thermal vias on the Top be connected only to top copper, or also to GND on 2?

[LJH]

Please refer to the latest datasheet, we will update DXF file.

[Panometric]

Thank you but Datasheet Pre-release v0.5 does not show the PCB layout at all so it's unclear.

@LJH Are all these answers correct?

1. Which document is correct?
Datasheet - ignore declaration of this area on dxf
2. For a 4 layer board where layer 2 is solid GND and 7.8 mil away from top, is it OK to leave GND on layer 2?
Yes, GND under any area that is not antenna is OK
3. IF NOT, Is it OK to locate components on the bottom in this area?
Yes, because GND area is almost continuous
4. Should the thermal vias on the Top be connected only to top copper, or also to GND on 2?
Connect 9 center pads to GND net, top and any other layer.