RSR.CCOUNT on Espressif's RISCs?

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vvb333007
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RSR.CCOUNT on Espressif's RISCs?

Postby vvb333007 » Fri Jul 18, 2025 9:52 am

Hello everyone!

On Xtensa-based CPUs one can use "rsr.ccount" assembler instruction to read CPU cycles count register.
Do we have something like that on C3, C6, P4 ?

Thanks!
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Slava.
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MicroController
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Re: RSR.CCOUNT on Espressif's RISCs?

Postby MicroController » Fri Jul 18, 2025 12:53 pm

Yup: MPCCR by default counts CPU cycles -> https://github.com/espressif/esp-idf/bl ... ils.h#L110
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