ESP32-P4 I2S Master - Issue with Alignment of data bits with bclk

[jmf111]

Hello,
I'm working on a USB to I2S bridge targeting 32 bits x 8 channels and 96kHz. It is to be based on ESP components esp_codec_dev and usb_device_uac. First implementation with i2s 16 bits stereo is working with my Codec, but I don't have sound when I configure usb_device_uac with 32 bits samples. I2S is configured in master mode.

With the logic analyzer I identified that I have data bits edges not in sync with the bclk falling edges. See first attachment.

Hoever on the same board and similar initialization, the i2s peripheral example has its data edges well synchronized with the bclk (same board, same pins, same measurement setup.

Both codes return same debug logs, so initialization seems similar and OK on both:
My code:
D (332) i2s_common: DMA malloc info: dma_desc_num = 8, dma_desc_buf_size = dma_frame_num * slot_num * data_bit_width = 768
D (342) i2s_std: Clock division info: [sclk] 40000000 Hz [mdiv] 3 49/192 [mclk] 12288000 Hz [bdiv] 4 [bclk] 3072000 Hz
D (352) i2s_common: MCLK is pinned to GPIO16 on I2S0
D (362) i2s_std: The tx channel on I2S0 has been initialized to STD mode successfully
D (362) i2s_common: i2s rx channel enabled
D (372) i2s_common: i2s tx channel enabled
W (372) DUMMY_CODEC: PA control disabled, gpio_if:0x4ff3d62c pa_pin:-1
D (382) i2s_common: i2s tx channel disabled
I (382) I2S_IF: Paired data: 0x4ff3f404, current mode: playback, paired in_enable: 0, paired out_enable: 0
D (392) i2s_std: Clock division info: [sclk] 40000000 Hz [mdiv] 3 49/192 [mclk] 12288000 Hz [bdiv] 4 [bclk] 3072000 Hz
I (402) I2S_IF: STD: TX, data_bit: 32, slot_bit: 32, ws_width: 32, slot_mode: STEREO, slot_mask: 0x3
I (412) I2S_IF: STD: TX, sample_rate_hz: 48000, mclk_multiple: 256, clk_src: 0
D (422) i2s_common: i2s tx channel enabled


Example code:
D (278) i2s_common: tx channel is registered on I2S0 successfully
D (278) i2s_common: rx channel is registered on I2S0 successfully
D (288) i2s_common: DMA malloc info: dma_desc_num = 6, dma_desc_buf_size = dma_frame_num * slot_num * data_bit_width = 1920
D (298) i2s_std: Clock division info: [sclk] 40000000 Hz [mdiv] 3 49/192 [mclk] 12288000 Hz [bdiv] 4 [bclk] 3072000 Hz
D (308) i2s_common: MCLK is pinned to GPIO16 on I2S0
D (308) i2s_std: The tx channel on I2S0 has been initialized to STD mode successfully
D (318) i2s_common: DMA malloc info: dma_desc_num = 6, dma_desc_buf_size = dma_frame_num * slot_num * data_bit_width = 1920
D (328) i2s_std: Clock division info: [sclk] 40000000 Hz [mdiv] 3 49/192 [mclk] 12288000 Hz [bdiv] 4 [bclk] 3072000 Hz
D (338) i2s_common: MCLK is pinned to GPIO16 on I2S0
D (348) i2s_std: The rx channel on I2S0 has been initialized to STD mode successfully
D (348) i2s_common: i2s rx channel enabled
D (358) i2s_common: i2s tx channel enabled

My code attached. For me the synch between data bits and bclk is done by the peripheral (hardware). I work on this since a week part time and I failed to identify:
- what can cause this those data bits not in synch with bclk in Master mode in my code,
- what is the difference that makes that the i2s example code is showing good behaviour, and not my code.

Help very welcomed to save the WeekEnd

Best regards,

JMF

Not OK one not synch

Capture d’écran 2026-07-24 212002 32bits 48k I2S debug.jpg (84.74 KiB) Viewed 20 times

i2s std example OK on same chip

Capture d’écran 2026-07-24 212002 32bits 48k I2S std correct.jpg (104.9 KiB) Viewed 20 times

[jmf111]

Hello,

I did additional tests. In my code, based on the usb_device_uac component and example, I was initializing the rx channel of the i2s ( i2s_new_channel(&chan_cfg, &i2s_tx_handle,&i2s_rx_handle))). Then I was initializing it (i2s_channel_init_std_mode(i2s_rx_handle, &std_cfg)) and enabling it (i2s_channel_enable(i2s_rx_handle)) before the tx channel. As the code was configured for 2 speakers channels and no inputs, the rx channel was not read by the code.

Removing the configuration of the rx channel from my code seems to address the issue: now the tx data bits edges are aligned with bclk.

Could it be some "interference" between the tx and rx channels of the peripheral ?

Best regards,
JMF

[jmf111]

I did some additional tests, re-activating the different i2s_rx setup:
- i2s_new_channel(&chan_cfg, &i2s_tx_handle,&i2s_rx_handle) => this does not creates an issue,
- i2s_channel_init_std_mode(i2s_rx_handle, &std_cfg) => There is an error when I try try to write using &i2s_tx_handle !!!! See attached printscreen,
- i2s_channel_enable(i2s_rx_handle) => Now the writes succeed, but the edges are not in sync with bclk.

I haven't seen in the documentation any instruction or warning preventing to configure the rx channel if we are not using it... I would be happy to better understand the issue.

Happy to learn if someone has ideas

Regards,
JMF

Error writing tx if rx is not enabled.jpg (65.28 KiB) Viewed 7 times

[MicroController]

In your code, you're initializing two channels with the same i2s_std_config_t; i.e. you tell two channels to use the same pins (like you would do for one full-duplex channel). This might be causing issues.